1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various examples of an integrated circuit product comprised of FinFET devices with single diffusion break isolation structures, and various methods of making such products.
2. Description of the Related Art
FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device 10 includes a plurality of trenches 14 that define three illustrative fins 16, a gate structure 18, sidewall spacers 20 and a gate cap layer 22. The fins 16 have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L of the fins 16 corresponds to the direction of current travel in the device 10 when it is operational. The portions of the fins 16 covered by the gate structure 18 are the channel regions of the FinFET device 10
A shallow trench isolation structure (not shown) is formed in the semiconducting substrate 12 around the FinFET device 10 so as to electrically isolate the FinFET device. Traditionally, isolation structures were always the first structures that were formed when manufacturing semiconductor devices. The isolation structures were formed by etching the trenches for the isolation structures and thereafter filling the trenches with the desired insulating material, e.g., silicon dioxide. Thereafter, the isolation structures were masked and the trenches 14 were etched into the substrate 12 so as to define the fins 16. However, as the dimensions of the fins became smaller, problems arose with manufacturing the isolation structures before the fins were formed. As one example, trying to accurately define very small fins in regions that were separated by relatively large isolation regions was difficult due to the non-uniform spacing between various structures on the substrate. One manufacturing technique that is employed in manufacturing FinFET devices is to initially form the trenches 14 in the substrate 12 to define multiple “fins” that extend across the entire wafer or substrate 12, and thereafter remove some of the fins 16 where isolation structures will be formed. Using this type of manufacturing approach, better accuracy and repeatability may be achieved in forming the fins 16 to very small dimensions due to the more uniform environment in which the etching process that forms the trenches 14 is performed.
The size or “footprint” of the fins 16 that are removed so that an isolation structure can be formed may vary in size, i.e., it may be very large (in a relative sense) or very small. In many applications, a section of several adjacent fins, positioned side-by-side, may be removed to make room for a portion of a relatively large isolation structure. In some product designs, only a portion of one single fin may be removed between two adjacent “active” fins to make room for an isolation structure that is to be formed between the two active fins. That is, considering three fins that are formed side-by-side with a uniform gate pitch for all three, a portion of the middle fin may be removed, thereby cutting the middle fin into two active fins. The amount of the middle fin removed in such a situation corresponds approximately to the gate length of a “dummy” gate structure that will be formed in and above the area of the removed portion of the middle fin. Such a configuration is sometimes referred to as a Single Diffusion Break (SDB), since the isolation material that will be formed where the portion of the middle fin is removed is the only means of preventing undesirable current flow between the two active fins that abut the SDB isolation structure.
One prior art fin removal process that is typically referred to as “Fins-cut-First,” will be described with reference to FIGS. 1B-1J. FIG. 1B depicts the device 10 after several process operations were performed. First, an etching process was performed through a patterned masking layer (not shown) so as to define the trenches 14 in the substrate 12 that define the fins 16. Then, a layer of insulating material 24, such as silicon dioxide, was formed so as to overfill the trenches 14. Thereafter, one or more chemical mechanical polishing (CMP) processes, mixed with one or more wet clean processes, were performed to planarize the upper surface of the insulating material 24 such that the process(es) stops on the top of the fins 16. Performing such operations results in the removal of the patterned hard mask and exposing the upper surface of the fins 16.
FIGS. 1C and 1D depict the device 10 after a patterned mask layer 26, e.g., a patterned photoresist mask, was formed above device 10. The patterned mask layer 26 has a plurality of openings 26A, each of which exposes a portion of the axial length of fins 16 that will be removed, i.e., the dimension 16AL, to form SDB isolation regions. The axial length 16AL of the fins 16 that are removed is normally kept as small as possible so as not to unnecessarily consume valuable plot space on the substrate 12 and it will normally be approximately equal to the gate length of a gate structure that will be formed above the area where the exposed portions of the fins are removed.
FIG. 1E depicts the device 10 after a timed etching process was performed through the patterned etch mask 26 to remove the exposed fins 16 and thereby define cavities 17 in the area formerly occupied by the removed fin portions. Typically, substantially the entire vertical height of the exposed fins is removed.
FIG. 1F depicts the device 10 after several process operations were performed. First, the patterned etch mask 26 was removed. Then, another layer of insulating material 19 was deposited so as to overfill the cavities 17. A CMP process was then performed to remove excess amounts of the insulating material 19 positioned outside of the fin cavities 17. In the drawings, the material 19 is provided with a different shading just to make clear that it is formed at a different point in time than the insulating material 24. In practice, the materials 24 and 19 are typically made of the same material, e.g., silicon dioxide.
FIG. 1G depicts the device 10 after a so-called “fin-reveal” etch-back process was performed to recess the layers of insulating material 19, 24 between the fins 16 and thereby expose the upper portions of the fins 16, which corresponds to the final fin height of the fins 16.
An alternative method to achieve the prior art device 10 depicted in FIG. 1G is to apply a two-times lithography technique on the etch mask 26 that, when combined with a corresponding etch process, opens the trench area and SDB isolation regions in the etch mask, respectively. Then, an etching process may be performed to form the shallow trenches and the SDB open areas between fins in the substrate 12. After overfilling the trenches 14 in FIG. 1A and the SDB open areas 17 in FIG. 1E with insulating material, such as silicon dioxide, one or more CMP processes, or wet clean processes, may be performed to remove the silicon dioxide above the mask layer 26, so as to finally obtain the substantially planar surface depicted in FIG. 1F. As shown, the top surface of the fin 16 is exposed such that it is approximately level with the upper surface of the insulating layer 24. Ultimately, the device 10 depicted in FIG. 1G may be obtained by performing a so called “fin-reveal” recess etch-back process, where the SDB isolation structures 19 and the insulating material 24 were recessed to approximately the same height level.
FIGS. 1H-1J depict the device after an illustrative dummy gate structure 30 was formed above the fins 16. In general, the gate structure 30 is comprised of a gate insulation layer 30A and a gate electrode 30B. The gate structure 30 may be made using either so-called gate-first manufacturing techniques or so-called replacement gate manufacturing techniques. Also depicted are an illustrative gate cap layer 32 and sidewall spacers 34. The dashed-circled regions 25 in FIG. 1H depict the locations where the portion of the fins was removed. As depicted for the middle region 25, the removal of the portion of the fin separates the fin 16 into a first active fin 16X and a second active fin 16Y. The dummy gate structure 30 is a “dummy” relative to the active fins 16X, 16Y in the sense that it is not the gate structure that controls the operation of either of the fins 16X, 16Y. The gate structures that control the operation of the devices that include the fins 16X, 16Y are not depicted in FIG. 1H. However, the gate structure 30 may be an operational gate structure for the fins 16 that have remaining portions positioned under the gate structure 30, as depicted by the dashed lines. FIG. 1J is a cross-sectional view that is taken through the long-axis of the fins 16X, 16Y. As depicted, given the relatively short height of the isolation region 19, due to it being formed after the fin cut process was performed and commonly recessed along with the layer of insulating material 24, there is a relatively short path 36 where undesirable diffusion may occur between the fins 16X and 16Y during operations.
One prior art technique that has been employed in an attempt to increase the height of the isolation material under the dummy gate structure 30 between the fins 16X, 16Y is simplistically depicted in FIG. 1K. As shown therein, this prior art method involved forming additional insulating material 40 in the area where the dummy gate structure 30 will be formed. However, this prior art method involved the use of a separate masking layer that permitted formation of the additional isolation material 40 selectively only in regions where such SDB situations were present. As is well known in the art, each additional masking layer that is required when forming an integrated circuit product results in increased manufacturing costs and time, both of which are undesirable.
The present disclosure is directed to various examples of an integrated circuit product comprised of FinFET devices with single diffusion break isolation structures, and various methods of making such products, that may solve or reduce one or more of the problems identified above.